MC68HC908QC16_07 Datasheet, PDF (47/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

MCU STOP
ADHWT
AD0
ADn
ADSCR
ADCLK
12
ADCK _CLOCK
CONTROL SEQUENCER
DIVIDE
Functional Description
ACLKEN
ASYNC
CLOCK
GENERATOR
ACLK
BUS CLOCK
ALTERNATE CLOCK SOURCE
ADVIN
SAR CONVERTER
AIEN 1
COCO ²
INTERRUPT
V_REFH
V_REFL
DATA REGISTERS ADRH:ADRL
Figure 3-2. ADC10 Block Diagram
The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The
output of the input multiplexer (ADVIN) is converted by a successive approximation algorithm into a 10-bit
digital result. When the conversion is completed, the result is placed in the data registers (ADRH and
ADRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADRL. The conversion complete flag
is then set and an interrupt request is generated if AIEN has been set.
3.3.1 Clock Select and Divide Circuit
The clock select and divide circuit selects one of three clock sources and divides it by a configurable value
to generate the input clock to the converter (ADCK). The clock can be selected from one of the following
sources:
• The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock
source which is enabled when the ADC10 is converting and the clock source is selected by setting
ACLKEN. When ADLPC is clear, this clock operates from 1–2 MHz; when ADLPC is set, it operates
at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop mode for lower
noise operation.
• Alternate Clock Source — This clock source is equal to the external oscillator clock or four times
the bus clock. The alternate clock source is MCU specific, see 3.1 Introduction to determine source
and availability of this clock source option. This clock is selected when ADICLK and ACLKEN are
both clear.
• The bus clock — This clock source is equal to the bus frequency. This clock is selected when
ADICLK is set and ACLKEN is clear.
Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If
the available clocks are too slow, the ADC10 will not perform according to specifications. If the available
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
47