MC68HC908QC16_07 Datasheet, PDF (146/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
PDS2
PDS1
PDS0 PSSB4 PSSB3 PSSB2 PSSB1
0
0
0
0
0
0
0
Figure 13-17. ESCI Prescaler Register (SCPSC)
Bit 0
PSSB0
0
PDS2–PDS0 — Prescaler Divisor Select Bits
These read/write bits select the prescaler divisor as shown in Table 13-8.
NOTE
The setting of ‘000’ will bypass this prescaler. Do not bypass the prescaler
while ENSCI is set, because unexpected results may occur.
Table 13-8. ESCI Prescaler Division Ratio
PDS[2:1:0]
000
001
010
011
100
101
110
111
Prescaler Divisor (PD)
Bypass this prescaler
2
3
4
5
6
7
8
PSSB4–PSSB0 — Clock Insertion Select Bits
These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average prescaler frequency as shown in Table 13-9.
Use the following formula to calculate the ESCI baud rate:
Frequency of the SCI clock source
Baud rate = _{64 x BPD x BD x (PD + PDFA)}
where:
SCI clock source = bus clock or BUSCLKX4 (selected by ESCIBDSRC in the configuration register)
BPD = Baud rate register prescaler divisor
BD = Baud rate divisor
PD = Prescaler divisor
PDFA = Prescaler divisor fine adjust
Table 13-10 shows the ESCI baud rates that can be generated with a 4.9152-MHz bus frequency.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
146
Freescale Semiconductor