MC68HC908QC16_07 Datasheet, PDF (217/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Registers
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
1
X
X
X
Table 17-2. Mode, Edge, and Level Selection
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Mode
Output preset
Input capture
Output compare
or PWM
Buffered output
compare or
buffered PWM
Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
NOTE
After initially enabling a TIM2 channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect.
1 = Channel x pin toggles on TIM2 counter overflow.
0 = Channel x pin does not toggle on TIM2 counter overflow.
NOTE
When TOVx is set, a counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As Figure 17-11 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
T2CHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 17-11. CHxMAX Latency
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
217