MC68HC908QC16_07 Datasheet, PDF (197/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

TIM1 During Break Interrupts
16.6 TIM1 During Break Interrupts
A break interrupt stops the counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
16.7 I/O Signals
The TIM1 module can share its pins with the general-purpose I/O pins. See Figure 16-1 for the port pins
that are shared.
16.7.1 TIM1 Channel I/O Pins (T1CH3:T1CH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 and T1CH2 can be configured as buffered output compare or buffered PWM pins.
16.7.2 TIM1 Clock Pin (T1CLK)
T1CLK is an external clock input that can be the clock source for the counter instead of the prescaled
internal bus clock. Select the T1CLK input by writing 1s to the three prescaler select bits, PS[2:0]. The
Timer Interface Module Characteristics table in the Electricals section. The maximum T1CLK frequency
is the least of 4 MHz or bus frequency ÷ 2.
16.8 Registers
The following registers control and monitor operation of the TIM1:
• TIM1 status and control register (T1SC)
• TIM1 control registers (T1CNTH:T1CNTL)
• TIM1 counter modulo registers (T1MODH:T1MODL)
• TIM1 channel status and control registers (T1SC0 through T1SC3)
• TIM1 channel registers (T1CH0H:T1CH0L through T1CH3H:T1CH3L)
16.8.1 TIM1 Status and Control Register
The TIM1 status and control register (T1SC) does the following:
• Enables TIM1 overflow interrupts
• Flags TIM1 overflows
• Stops the counter
• Resets the counter
• Prescales the counter clock
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
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