MC68HC908QC16_07 Datasheet, PDF (184/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
MISO/MOSI
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
BYTE 1
BYTE 2
BYTE 3
Figure 15-12. CPHA/SS Timing
NOTE
A high on the SS pin of a slave SPI puts the MISO pin in a high-impedance
state. The slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See 15.3.6.2 Mode Fault Error.) For the state
of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN
bit is 0 for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. When MODFEN is 1, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
User software can read the state of the SS pin by configuring the appropriate pin as an input and reading
the port data register. See Table 15-2.
Table 15-2. SPI Configuration
SPE
0
1
1
1
SPMSTR
X⁽¹⁾
0
1
1
1. X = Don’t care
MODFEN
X
X
0
1
SPI Configuration
Not enabled
Slave
Master without MODF
Master with MODF
Function of SS Pin
General-purpose I/O; SS ignored by SPI
Input-only to SPI
General-purpose I/O; SS ignored by SPI
Input-only to SPI
15.8 Registers
The following registers allow the user to control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
15.8.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
184
Freescale Semiconductor