MC68HC908QC16_07 Datasheet, PDF (138/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
PTY — Parity Bit
This read/write bit determines whether the ESCI generates and checks for odd parity or even parity
(see Table 13-4).
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
13.8.2 ESCI Control Register 2
ESCI control register 2 (SCC2):
• Enables these interrupt requests:
– SCTE bit to generate transmitter interrupt requests
– TC bit to generate transmitter interrupt requests
– SCRF bit to generate receiver interrupt requests
– IDLE bit to generate receiver interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables ESCI wakeup
• Transmits ESCI break characters
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 13-10. ESCI Control Register 2 (SCC2)
SCTIE — ESCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate ESCI transmitter interrupt requests. Setting the
SCTIE bit in SCC2 enables the SCTE bit to generate interrupt requests.
1 = SCTE enabled to generate interrupt
0 = SCTE not enabled to generate interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate ESCI transmitter interrupt requests.
1 = TC enabled to generate interrupt requests
0 = TC not enabled to generate interrupt requests
SCRIE — ESCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate ESCI receiver interrupt requests. Setting the
SCRIE bit in SCC2 enables the SCRF bit to generate interrupt requests.
1 = SCRF enabled to generate interrupt
0 = SCRF not enabled to generate interrupt
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
138
Freescale Semiconductor