MC68HC908QC16_07 Datasheet, PDF (110/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Ports (PORTS)
Table 11-1 summarizes the operation of the port A pins.
Table 11-1. Port A Pin Functions
PTAPUE
Bit
1
0
X
DDRA
Bit
0
0
1
PTA
Bit
X⁽¹⁾
X
X
I/O Pin
Mode
Input, V_DD(2)
Input, Hi-Z⁽⁴⁾
Output
Accesses to DDRA
Read/Write
DDRA5–DDRA0
DDRA5–DDRA0
DDRA5–DDRA0
1. X = don’t care
2. I/O pin pulled to V_DD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2
Accesses to PTA
Read
Write
Pin
PTA5–PTA0⁽³⁾
Pin
PTA5–PTA0⁽³⁾
PTA5–PTA0
PTA5–PTA0⁽⁵⁾
11.4 Port B
Port B is an 8-bit general purpose I/O port. Each port B pin can be configured to have an internal pullup
when used as an input port pin.
11.4.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
Read:
Write:
Reset:
Bit 7
PTB7
6
PTB6
5
PTB5
4
3
PTB4
PTB3
Unaffected by reset
2
PTB2
1
PTB1
Bit 0
PTB0
Figure 11-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
11.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Read:
Write:
Reset:
Bit 7
DDRB7
0
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Figure 11-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
110
Freescale Semiconductor