MC68HC908QC16_07 Datasheet, PDF (201/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Read:
Write:
Reset:
Bit 7
CH0F
0
0
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Figure 16-9. TIM1 Channel 0 Status and Control Register (T1SC0)
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
Figure 16-10. TIM1 Channel 1 Status and Control Register (T1SC1)
Registers
Read:
Write:
Reset:
Bit 7
CH2F
0
0
6
CH2IE
0
5
MS2B
0
4
MS2A
0
3
ELS2B
0
2
ELS2A
0
1
TOV2
0
Bit 0
CH2MAX
0
Figure 16-11. TIM1 Channel 2 Status and Control Register (T1SC2)
Read:
Write:
Reset:
Bit 7
CH3F
0
0
6
5
0
CH3IE
0
0
= Unimplemented
4
MS3A
0
3
ELS3B
0
2
ELS3A
0
1
TOV3
0
Bit 0
CH3MAX
0
Figure 16-12. TIM1 Channel 3 Status and Control Register (T1SC3)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
counter registers matches the value in the TIM1 channel x registers.
Clear CHxF by reading the T1SCx register with CHxF set and then writing a 0 to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM1 interrupt service requests on channel x.
1 = Channel x interrupt requests enabled
0 = Channel x interrupt requests disabled
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
201