MC68HC908QC16_07 Datasheet, PDF (127/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

INTERNAL BUS
Functional Description
÷4
SCP1
SCP0
SCR2
SCR1
SCR0
PRE-
BAUD
SCALER DIVIDER
÷ 16
ESCI DATA REGISTER
11-BIT
TRANSMIT
SHIFT REGISTER
STOP 8 7 6 5 4 3 2 1 0 START
TXINV
SCI_TxD
BUSCLKX4
OR
BUS CLOCK
PDS2
PDS1
PDS0
PSSB4
PSSB3
PSSB2
PSSB1
PSSB0
TRANSMITTER
INTERRUPT REQUEST
M
PEN
PARITY
PTY
GENERATION
T8
TRANSMITTER
CONTROL LOGIC
SCTE
SCTE
SCTIE
TC
TCIE
SCTIE
TC
TCIE
Figure 13-4. ESCI Transmitter
SBK
LOOPS
ENSCI
TE
LINT
13.3.2.3 Break Characters
Writing a 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character.
For TXINV = 0 (output not inverted), a transmitted break character contains all 0s and has no start, stop,
or parity bit. Break character length depends on the M bit in SCC1 and the LINR bits in SCBR. As long as
SBK is set, transmitter logic continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the last break character and then
transmits at least one 1. The automatic 1 at the end of a break character guarantees the recognition of
the start bit of the next character.
When LINR is cleared in SCBR, the ESCI recognizes a break character when a start bit is followed by
eight or nine 0 data bits and a 0 where the stop bit should be, resulting in a total of 10 or 11 consecutive
0 data bits. When LINR is set in SCBR, the ESCI recognizes a break character when a start bit is followed
by 9 or 10 0 data bits and a 0 where the stop bit should be, resulting in a total of 11 or 12 consecutive 0
data bits.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
127