MC68HC908QC16_07 Datasheet, PDF (119/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

PWU During Break Interrupts
12.5.2 Stop Mode
The PWU module remains active in stop mode while the PWUON and SMODE bits in PWUSC is set.
Setting PWUIE in PWUSC enables PWU interrupts to bring the MCU out of stop mode.
12.6 PWU During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
12.7 I/O Signals
The PWU module is not associated with any external I/O pins.
12.8 Registers
The PWU registers control and monitor operation of the PWU. The registers that are relevant to the use
of the PWU are as follows.
• Periodic wakeup status and control register (PWUSC)
• Periodic wakeup prescaler register (PWUP)
• Periodic wakeup modulo register (PWUMOD)
12.8.1 Periodic Wakeup Status and Control Register
The PWUSC register contains bits that:
• Enables or disables the periodic wakeup module
• Selects the clock source to the periodic wakeup prescaler register
• Flags periodic wakeup interrupt requests
• Acknowledges periodic wakeup interrupts
• Enables or disables periodic wakeup interrupts
• Enables or disables the module during stop mode
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
PWUF
0
PWUON PWUCLKSEL
PWUIE SMODE
PWUACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-2. Periodic Wakeup Status and Control Register (PWUSC)
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
119