MC68HC908QC16_07 Datasheet, PDF (208/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM2)
An unsynchronized write to the TIM2 channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM2 overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM2 may pass the new value before it is
written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable TIM2 overflow interrupts and write the
new value in the TIM2 overflow interrupt routine. The TIM2 overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an output compare interrupt routine
(at the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
17.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
T2CH0 pin. The TIM2 channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM2 channel 0 status and control register (T2SC0) links channel 0 and channel
1. The output compare value in the TIM2 channel 0 registers initially controls the output on the T2CH0
pin. Writing to the TIM2 channel 1 registers enables the TIM2 channel 1 registers to synchronously control
the output after the TIM2 overflows. At each subsequent overflow, the TIM2 channel registers (0 or 1) that
control the output are the ones written to last. T2SC0 controls and monitors the buffered output compare
function, and TIM2 channel 1 status and control register (T2SC1) is unused. While the MS0B bit is set,
the channel 1 pin, T2CH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
17.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM2 can generate a PWM
signal. The value in the TIM2 counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM2 counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 17-3 shows, the output compare value in the TIM2 channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM2
to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the
TIM2 to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1).
The value in the TIM2 counter modulo registers and the selected prescaler output determines the
frequency of the PWM output The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
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