MC68HC908QC16_07 Datasheet, PDF (185/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Registers
Read:
Write:
Reset:
Bit 7
SPRIE
0
R
6
5
R
SPMSTR
0
1
= Reserved
4
CPOL
0
3
2
1
CPHA SPWOM SPE
1
0
0
Bit 0
SPTIE
0
Figure 15-13. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables interrupt requests generated by the SPRF bit. The SPRF bit is set when a
byte transfers from the shift register to the receive data register.
1 = SPRF interrupt requests enabled
0 = SPRF interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 15-4 and Figure 15-6.) To transmit data between SPI modules, the SPI modules must have
identical CPOL values.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 15-4 and Figure 15-6.) To transmit data between SPI modules, the SPI modules must have
identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be high between
bytes. (See Figure 15-12.)
SPWOM — SPI Wired-OR Mode Bit
This read/write bit configures pins SPSCK, MOSI, and MISO so that these pins become open-drain
outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 15.3.5
Resetting the SPI.)
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register.
1 = SPTE interrupt requests enabled
0 = SPTE interrupt requests disabled
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
185