MC68HC908QC16_07 Datasheet, PDF (199/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Registers
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the counter as
Table 16-1 shows.
Table 16-1. Prescaler Selection
PS2
PS1
PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TIM1 Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
T1CLK (if available)
16.8.2 TIM1 Counter Registers
The two read-only TIM1 counter registers contain the high and low bytes of the value in the counter.
Reading the high byte (T1CNTH) latches the contents of the low byte (T1CNTL) into a buffer. Subsequent
reads of T1CNTH do not affect the latched T1CNTL value until T1CNTL is read. Reset clears the TIM1
counter registers. Setting the TIM1 reset bit (TRST) also clears the TIM1 counter registers.
NOTE
If you read T1CNTH during a break interrupt, be sure to unlatch T1CNTL
by reading T1CNTL before exiting the break interrupt. Otherwise, T1CNTL
retains the value latched during the break.
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 16-5. TIM1 Counter High Register (T1CNTH)
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-6. TIM1 Counter Low Register (T1CNTL)
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
199