MC68HC908QC16_07 Datasheet, PDF (111/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 11-7 shows the
port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBPUEx
PULLUP
PTBx
READ PTB ($0001)
Port B
Figure 11-7. Port B I/O Circuit
When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading
address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
11.4.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each
of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRBx bit is configured as output.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 11-8. Port B Input Pullup Enable Register (PTBPUE)
PTBPUE[7:0] — Port B Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port B pins
1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0
0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its
DDRB bit.
Table 11-2 summarizes the operation of the port B pins.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
111