MC68HC908QC16_07 Datasheet, PDF (144/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
13.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the ESCI data register.
Bit 7
6
5
4
3
2
1
Bit 0
Read: R7
R6
R5
R4
R3
R2
R1
R0
Write: T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 13-15. ESCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading SCDR accesses the read-only received data bits, R7:R0.
Writing to SCDR writes the data to be transmitted, T7:T0.
NOTE
Do not use read-modify-write instructions on the ESCI data register.
13.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
NOTE
There are two prescalers available to adjust the baud rate — one in the
ESCI baud rate register and one in the ESCI prescaler register.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
LINT
LINR
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
R
= Reserved
Figure 13-16. ESCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
LINT — LIN Transmit Enable
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in Table 13-5.
LINR — LIN Receiver Bits
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in Table 13-5.
In LIN (version 1.2 and later) systems, the master node transmits a break character which will appear
as 11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Because a slave node cannot know
if it is running faster or slower than the master node (prior to synchronization), the LINR bit allows the
slave node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits.
The break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
144
Freescale Semiconductor