MC68HC908QC16_07 Datasheet, PDF (114/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Ports (PORTS)
11.5.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the four port C pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRCx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRCx bit is configured as output.
Bit 7
Read: 0
Write:
Reset: 0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
Bit 0
0
PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
0
0
0
0
0
Figure 11-12. Port C Input Pullup Enable Register (PTCPUE)
PTCPUE[3:0] — Port C Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port C pins
1 = Corresponding port C pin configured to have internal pull if its DDRC bit is set to 0
0 = Pullup device is disconnected on the corresponding port C pin regardless of the state of its
DDRC bit.
Table 11-3 summarizes the operation of the port C pins.
Table 11-3. Port C Pin Functions
PTCPUE
Bit
1
0
X
DDRC
Bit
0
0
1
PTC
Bit
X⁽¹⁾
X
X
I/O Pin
Mode
Input, V_DD(2)
Input, Hi-Z⁽⁴⁾
Output
Accesses to DDRC
Read/Write
DDRC2–DDRC0
DDRC2–DDRC0
DDRC2–DDRC0
1. X = don’t care
2. I/O pin pulled to V_DD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
Accesses to PTC
Read
Write
Pin
PTC3–PTC0⁽³⁾
Pin
PTC3–PTC0⁽³⁾
PTC3–PTC0
PTC3–PTC0
11.6 Port D
Port D is an 8-bit general purpose I/O port. Each port D pin can be configured to have an internal pullup
when used as an input port pin.
11.6.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
Read:
Write:
Reset:
Bit 7
PTD7
6
5
4
3
2
1
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
Unaffected by reset
Figure 11-13. Port D Data Register (PTD)
Bit 0
PTD0
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
114
Freescale Semiconductor