MC68HC908QC16_07 Datasheet, PDF (203/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Registers
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin T1CHx is
available as a general-purpose I/O pin. Table 16-2 shows how ELSxB and ELSxA work.
NOTE
After initially enabling a TIM1 channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect.
1 = Channel x pin toggles on counter overflow.
0 = Channel x pin does not toggle on counter overflow.
NOTE
When TOVx is set, a counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As Figure 16-13 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
T1CHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 16-13. CHxMAX Latency
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
203