MC68HC908QC16_07 Datasheet, PDF (193/274 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
output after the TIM1 overflows. At each subsequent overflow, the TIM1 channel registers (0 or 1) that
control the output are the ones written to last. T1SC0 controls and monitors the buffered output compare
function, and TIM1 channel 1 status and control register (T1SC1) is unused. While the MS0B bit is set,
the channel 1 pin, T1CH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the
T1CH2 pin. The TIM1 channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM1 channel 2 status and control register (T1SC2) links channel 2 and channel 3.
The output compare value in the TIM1 channel 2 registers initially controls the output on the T1CH2 pin.
Writing to the TIM1 channel 3 registers enables the TIM1 channel 3 registers to synchronously control the
output after the TIM1 overflows. At each subsequent overflow, the TIM1 channel registers (2 or 3) that
control the output are the ones written to last. T1SC2 controls and monitors the buffered output compare
function, and TIM1 channel 3 status and control register (T1SC3) is unused. While the MS2B bit is set,
the channel 3 pin, T1CH3, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
16.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM1 can generate a PWM
signal. The value in the TIM1 counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM1 counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 16-3 shows, the output compare value in the TIM1 channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM1
to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the
TIM1 to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1).
OVERFLOW
OVERFLOW
POLARITY = 1
(ELSxA = 0) T1CHx
POLARITY = 0 T1CHx
(ELSxA = 1)
PERIOD
PULSE
WIDTH
OVERFLOW
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 16-3. PWM Period and Pulse Width
OUTPUT
COMPARE
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 3
Freescale Semiconductor
193