XRT83L34_05 Datasheet, PDF (94/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FIGURE 33. RECEIVE CLOCK AND OUTPUT DATA TIMING
R_DY
RCLK_R
RCLK_F
RCLK
RPOS
or
RNEG
R_HO
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. The inter-
face timing shown in Figure 34 and Figure 36 is described in Table 50.
FIGURE 34. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
ALE_AS
A D D R [6 :0 ]
CS
D A T A [7 :0 ]
RD_DS
W R_R/W
RDY_DTACK
t₀
t₅
t₁
READ OPERATIO N
Valid Address
Valid Data for Readback
t₂
W RITE OPERATION
t₀
t₅
Valid Address
Data Available to W rite Into the LIU
t₃
t₄
91