XRT83L34_05 Datasheet, PDF (39/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER (CHANNELS 0 - 3)
INTERNAL RECEIVE TERMINATION MODE
In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive
channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83L34 is set for external termination mode at power up or at Hardware reset.
TABLE 6: RECEIVE TERMINATION CONTROL
RXTSEL
RX TERMINATION
0
EXTERNAL
1
INTERNAL
In Host mode, bit 7 in the appropriate channel register, (Table 21, “Microprocessor Register #1, Bit
Description,” on page 64), is set “High” to select the internal termination mode for that specific receive channel.
FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE
TPOS
TNEG
TCLK
TX
Line Driver
RPOS
RNEG
RCLK
RX
Equalizer
Channel _n
R _int
TTIP
0.68µ F
1
T1 ₅
TRING
R _int
RTIP
R _int
RRING
4
8
1:2
5
T2 ₁
8
4
1:1
TTIP
75 Ω, 100 Ω
110 Ω or 120 Ω
TRING
RTIP
75 Ω, 100 Ω
110 Ω or 120 Ω
RRING
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in Table 7.
NOTE: In Hardware mode, pins RXRES[1:0] control all channels.
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