XRT83L34_05 Datasheet, PDF (25/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
SIGNAL NAME
TRATIO
INT
RESET
SR/DR
LOOP1_0
LOOP0_0
LOOP1_1
LOOP0_1
LOOP1_2
LOOP0_2
LOOP1_3
LOOP0_3
PIN #
119
121
16
42
43
44
45
46
47
48
49
TYPE
I
O
I
I
I/O
DESCRIPTION
Transmitter Transformer Ratio Select - Hardware Mode
In external termination mode (TXSEL = 0), setting this pin "High" selects a
transformer ratio of 1:2 for the transmitter. A "Low" on this pin sets the trans-
mitter transformer ratio to 1:2.45. In the internal termination mode the
transmitter transformer ratio is permanently set to 1:2 and the state of this pin
is ignored.
Interrupt Output - Host Mode
This pin is asserted “Low” to indicate an alarm condition. See “Micropro-
cessor Interface” on page 13.
NOTE: This pin is an open drain output and requires an external 10kΩ pull-
up resistor.
Hardware Reset (Active "Low")
When this pin is tied “Low” for more than 10µs, the device is put in the reset
state.
Pulling RESET and ICT pins “Low” simultaneously will put the chip in factory
test mode. This condition should not be permitted during normal operation.
NOTE: Internally pulled “High” with a 50kΩ resistor.
Single-Rail/Dual-Rail Data Format
Connect this pin "Low" to select transmit and receive data format in Dual-rail
mode. In this mode, HDB3 or B8ZS encoder and decoder are not available.
Connect this pin "High" to select single-rail data format.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
Loop-Back Control Pins - Hardware Mode:
Loop-back control pin 1 - Channel _0
Loop-back control pin 0 - Channel _0
Loop-back control pin 1 - Channel _1
Loop-back control pin 0 - Channel _1
Loop-back control pin 1 - Channel _2
Loop-back control pin 0 - Channel _2
Loop-back control pin 1 - Channel _3
Loop-back control pin 0 - Channel _3
LOOP1_n
0
0
1
1
LOOP0_n
MODE
0
Normal Mode No Loop-back Channel_n
1
Local Loop-Back Channel_n
0
Remote Loop-Back Channel_n
1
Digital Loop-Back Channel_n
D[7]
42
D[6]
43
D[5]
44
D[4]
45
D[3]
46
D[2]
47
D[1]
48
D[0]
49
Microprocessor R/W Data bits [7:0] - Host Mode
These pins are microprocessor data bus pins. See “Bi-Directional Data
Bus Pins/Loop-back Control Input Pins - D[7:0]:” on page 17.
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
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