XRT83L34_05 Datasheet, PDF (20/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
µPTS1
µPTS2
PIN #
106
107
TYPE
I
DESCRIPTION
Microprocessor Type Select Input Pins/Receive Clock Edge Select/
Transmit Clock Edge Select Input Pin:
The exact function of these input pins depends upon whether the XRT83L34
device has been configured to operate in the HOST or Hardware Mode, as
described below.
HOST Mode Operation - Microprocessor Type Select Input Bits 2 and 1 -
µPTS[2:1]:
These two input pins permit the user to configure the Microprocessor Inter-
face to operate in either of the following modes.
• Intel-Asynchronous Mode
• Motorola-Asynchronous Mode
The relationship between the settings of these input pins and the corre-
sponding Microprocessor Interface configuration is presented below.
µPTS2
0
0
µPTS1
0
1
µP Type
Intel Asynchronous Mode
Motorola Asynchronous Mode
RCLKE
TCLKE
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]/
D[1]/
D[0]/
LOOP1_0
LOOP0_0
LOOP1_1
LOOP0_1
LOOP1_2
LOOP0_2
LOOP1_3
LOOP0_3
NOTE: The µPTS2 (pin107) should be tied to GND. The µPTS1(pin 106)
input pin permits the user to selects either the Intel-Asynchronous or
the Motorola Asynchronous Modes.
Hardware Mode Operation - Receive Clock Edge Select Input pin:
106
See “Receive Clock Edge Select/Microprocessor Type Select Input
pin:” on page 8.
Hardware Mode Operation - Transmit Clock Edge Select Input pin:
107
See “Transmit Clock Edge - Hardware Mode” on page 9.
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
42
I/O Bi-Directional Data Bus Pins/Loop-back Control Input Pins - D[7:0]:
43
The exact function of these input/output pins depends upon whether the
44
XRT83L34 device has been configured to operate in the HOST or Hardware
45
Mode, as described below.
46
HOST Mode Operation - Bi-Directional Data Bus Input/Output Pins
47
(Microprocessor Interface block) - D[7:0]:
These pins are used to drive and receive data over the bi-directional data
48
bus, whenever the Microprocessor performs a READ or WRITE operation
49
with the Microprocessor Interface of the XRT83L34 device.
42
Hardware Mode Operation - Loop-back Control pin, Bits
43
[1:0]_Channel_n - Hardware Mode
44
Pins 42 - 49 control which Loop-Back mode is selected per channel. See
45
“Loop-Back Control Pins - Hardware Mode:” on page 22.
46
NOTE: Internally pulled “Low” with a 50kΩ resistor.
47
48
49
17