XRT83L34_05 Datasheet, PDF (85/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 37: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION
D2
RXMUTE Receive Output Mute: Writing a “1” to this bit, mutes receive R/W
0
outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for
any channel that detects an RLOS condition.
NOTE: RCLK is not muted.
D1
EXLOS Extended LOS: Writing a “1” to this bit extends the number of R/W
0
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
D0
ICT
In-Circuit-Testing: Writing a “1” to this bit configures all the
R/W
0
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to “1” is equivalent to connecting
the Hardware ICT pin 88 to ground.
TABLE 38: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION
REGISTER ADDRESS
1000010
BIT #
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
D7
GAUGE1 Wire Gauge Selector Bit 1:
R/W
0
This bit together with bit D6 are used to select wire gauge size
as shown in the table below.
GAUGE1 GAUGE0
Wire Size
0
0
22 and 24 Gauge
0
1
22 Gauge
1
0
24 Gauge
1
1
26 Gauge
D6
GAUGE0 Wire Gauge Selector Bit 0:
See bit D7.
R/W
0
D5
TXONCNTL Transmit On Control:
R/W
0
In Host mode, setting this bit to “1” transfers the control of the
Transmit On/Off function to the TXON_n Hardware control
pins.
NOTE: This provides a faster On/Off capability for redundancy
application.
D4
TERCNTL Termination Control.
R/W
0
In Host mode, setting this bit to “1” transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.
NOTE: This provides a faster On/Off capability for redundancy
application.
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