XRT83L34_05 Datasheet, PDF (68/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 21: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION
D3
JASEL1_n Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits R/W
0
are used to disable or place the jitter attenuator of each chan-
nel independently in the transmit or receive path.
JASEL1
bit D3
0
0
1
1
JASEL0
bit D2
JA Path
0
JA Disabled
1
JA in Transmit Path
0
JA in Receive Path
1
JA in Receive Path
D2
JASEL0_n Jitter Attenuator select bit 0: See description of bit D3 for the R/W
0
function of this bit.
D1
JABW_n Jitter Attenuator Bandwidth Select: In E1 mode, set this bit R/W
0
to “1” to select a 1.5Hz Bandwidth for the Jitter Attenuator. The
FIFO length will be automatically set to 64 bits. Set this bit to
“0” to select 10Hz Bandwidth for the Jitter Attenuator in E1
mode. In T1 mode the Jitter Attenuator Bandwidth is perma-
nently set to 3Hz, and the state of this bit has no effect on the
Bandwidth.
Mode
T1
T1
T1
T1
E1
E1
E1
E1
JABW
bit D1
0
0
1
1
0
0
1
1
FIFOS_n
bit D0
0
1
0
1
0
1
0
1
JA B-W
Hz
3
3
3
3
10
10
1.5
1.5
FIFO
Size
32
64
32
64
32
64
64
64
D0
FIFOS_n FIFO Size Select: See table of bit D1 above for the function of R/W
0
this bit.
65