XRT83L34_05 Datasheet, PDF (77/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 27: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION
REGISTER ADDRESS
0000111
0010111
0100111
0110111
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
RO
0
D6
Reserved
RO
0
D5
CLOS5_n Cable Loss bit 5: CLOS[5:0]_n are the six bit receive selec-
RO
0
tive equalizer setting which is also a binary word that repre-
sents the cable attenuation indication within ±1dB. CLOS5_n
is the most significant bit (MSB) and CLOS0_n is the least sig-
nificant bit (LSB).
D4
CLOS4_n Cable Loss bit 4: See description of D5 for function of this bit. RO
0
D3
CLOS3_n Cable Loss bit 3: See description of D5 for function of this bit. RO
0
D2
CLOS2_n Cable Loss bit 2: See description of D5 for function of this bit. RO
0
D1
CLOS1_n Cable Loss bit 1: See description of D5 for function of this bit. RO
0
D0
CLOS0_n Cable Loss bit 0: See description of D5 for function of this bit. RO
0
74