XRT83L34_05 Datasheet, PDF (30/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 1: MASTER CLOCK GENERATOR
MCLKE1
KHZ
2048
2048
2048
1544
1544
2048
8
8
16
16
56
56
64
64
128
128
256
256
MCLKT1
KHZ
2048
2048
1544
1544
1544
1544
x
x
x
x
x
x
x
x
x
x
x
x
CLKSEL2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKSEL1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLKSEL0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MCLKRATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MASTER CLOCK
KHZ
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital
phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of
input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.
In Hardware mode only, all receive channels are turned on upon power-up and are always on. In Host mode,
each receiver channel can be individually turned on or off with the respective channel RXON_n bit. See
“Microprocessor Register #0, Bit Description” on page 63.
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