XRT83L34_05 Datasheet, PDF (54/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
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REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION
WR_R/W
Write Strobe/Read-Write Operation Identifier:
The exact function of this input pin depends upon which mode the Microprocessor Interface has been
configured to operate in, as described below.
Intel-Asynchronous Mode - Write Strobe Input - WR*:
If the Microprocessor Interface is configured to operate in the Intel-Asynchronous Mode, then this
input pin functions as the WR* (Active-Low, Write Strobe) input signal form the Microprocessor. Once
this active-low signal is asserted then the input buffers (associated with the Bi-Directional Data Bus
pins, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents of the Bi-Directional
Data Bus (into the "target" register or address location, within the XRT83L34 device) upon the rising
edge of this input pin.
Motorola-Asynchronous Mode - Read/Write Operation Identification Input - R/W*
If the Microprocessor Interface is operating in the "Motorola-Asynchronous" Mode, then this pin is
functionally equivalent to the "R/W*" input pin. In the Motorola-Asynchoronous Mode, a READ opera-
tion occurs if this pin is held at a logic "1", coincident to a falling edge of the RD/DS* (Data Strobe)
input pin. Similarly, a WRITE operation occurs if this pin is at a logic "0", coincident to a falling edge of
the RD/DS* (Data Strobe) input pin.
RDY_DTACK
Ready or DTACK (Data Transfer Acknowledge) Output pin:
The exact function of this output pin depends upon which mode the Microprocessor Interface has
been configured to operate in, as described below.
Intel-Asynchronous Mode - READY Output - RDY*:
If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then
this output pin will function as the "Active-low" READY Output:
During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the
logic low level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the cur-
rent READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a
logic "HIGH" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it
detects this output pin being toggled to the logic "LOW" level.
Motorola-Asynchronous Mode - Data Transfer Acknowledge Output - DTACK*:
If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode,
then this output pin will function as the "active-low" DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface will toggle this output pin to the logic
"LOW" level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the cur-
rent READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled
to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE
cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a
logic "HIGH" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it
detects this output pin being toggled to the logic "LOW" level.
INT
Interrupt Output:
This active-low output signal will be asserted (pulled to a logic "LOW" level) whenever the XRT83L34
device is requesting interrupt service from the Microprocessor. The activation of this pin can be
blocked by setting the GIE bit to “0” in the Command Control register.
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