XRT83L34_05 Datasheet, PDF (84/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 37: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION
REGISTER ADDRESS
1000001
BIT #
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
D7
E1arben E1 Arbitrary Pulse Enable
R/W
0
This bit is used to enable the Arbitrary Pulse Generators for
shaping the transmit pulse shape when E1 mode is selected.
If this bit is set to "1", all 8 channels will be configured for the
Arbitrary Mode. However, each channel is individually con-
trolled by programming the channel registers 0xn8 through
0xnF, where n is the number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
D6
CLKSEL2 Clock Select Inputs for Master Clock Synthesizer bit 2:
R/W
0
In Host mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
MCLKE1 MCLKT1
kHz
kHz
2048
2048
2048
2048
2048
1544
1544
1544
1544
1544
2048
1544
8
X
8
X
16
X
16
X
56
X
56
X
64
X
64
X
128
X
128
X
256
X
256
X
CLKSEL2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKSEL1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLKSEL0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MCLKRATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKOUT/
kHz
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.
D5
CLKSEL1 Clock Select inputs for Master Clock Synthesizer bit 1:
R/W
0
See description of bit D6 for function of this bit.
D4
CLKSEL0 Clock Select inputs for Master Clock Synthesizer bit 0:
R/W
0
See description of bit D6 for function of this bit.
D3
MCLKRATE Master clock Rate Select: The state of this bit programs the R/W
0
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =
“1”.
81