XRT83L34_05 Datasheet, PDF (63/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
MICROPROCESSOR REGISTER TABLES
The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 7 bit
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in Table 18 and Table 19 respectively.
REGISTER NUMBER
0 - 15
16 - 31
32 - 47
48 - 63
64 - 67
68 - 75
76-125
126
127
TABLE 18: MICROPROCESSOR REGISTER ADDRESS
REGISTER ADDRESS
HEX
BINARY
FUNCTION
0x00 - 0x0F
0000000 - 0001111
Channel 0 Control Registers
0x10 -0x1F
0010000 - 0011111
Channel 1 Control Registers
0x20 - 0x2F
0100000 - 0101111
Channel 2 Control Registers
0x30 - 0x3F
0110000 - 0111111
Channel 3 Control Registers
0x40 - 0x43
1000000 - 1000011
Command Control Registers for All 4 Channels
0x44 - 0x4B
1000100 - 1001011
R/W registers reserved for testing purpose.
0x4C - 0x7D
1001100 - 1111101
Reserved
0x7E
1111110
Device ID
0x7F
1111111
Device Revision ID
TABLE 19: MICROPROCESSOR REGISTER BIT DESCRIPTION
REG. #
ADDRESS
REG.
TYPE
BIT 7
BIT 6
BIT 5
BIT 4
Channel 0 Control Registers
0
0000000 R/W Reserved Reserved
RXON_n
Hex 0x00
EQC4_n
1
0000001 R/W RXTSEL_n TXTSEL_n TERSEL1_n TERSEL0_n
Hex 0x01
2
0000010 R/W INVQRSS_n TXTEST2_n TXTEST1_n TXTEST0_n
Hex 0x02
3
0000011 R/W NLCDE1_n NLCDE0_n CODES_n RXRES1_n
Hex 0x03
4
0000100 R/W Reserved DMOIE_n
FLSIE_n
LCVIE_n
Hex 0x04
5
0000101 RO Reserved
DMO_n
Hex 0x05
FLS_n
LCV_n
6
0000110 RUR Reserved DMOIS_n
FLSIS_n
LCVIS_n
Hex 0x06
7
0000111 RO Reserved Reserved CLOS5_n
CLOS4_n
Hex 0x07
8
0001000 R/W
X
Hex 0x08
B6S1_n
B5S1_n
B4S1_n
BIT 3
EQC3_n
JASEL1_n
TXON_n
RXRES0_n
NLCDIE_n
NLCD_n
NLCDIS_n
CLOS3_n
B3S1_n
BIT 2
EQC2_n
JASEL0_n
LOOP2_n
INSBPV_n
AISDIE_n
AISD_n
AISDIS_n
CLOS2_n
B2S1_n
BIT 1
BIT 0
EQC1_n
EQC0_n
JABW_n
FIFOS_n
LOOP1_n LOOP0_n
INSBER_n TRATIO_n
RLOSIE_n QRPDIE_n
RLOS_n
QRPD_n
RLOSIS_n QRPDIS_n
CLOS1_n CLOS0_n
B1S1_n
B0S1_n
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