XRT83L34_05 Datasheet, PDF (15/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
SIGNAL NAME
TCLK_0
TCLK_1
TCLK_2
TCLK_3
PIN #
1
128
103
102
TYPE
I
DESCRIPTION
Transmit Line Clock Input - Channel n:
The Transmit Section of Channel n will use this input pin to sample and latch
the data that is present on the "TPOS_n/TDATA_n" and "TNEG_n" input pins.
This input clock signal also functions as the timing source for the "Transmit
Direction" signal within the Channel.
For T1 Applications, the user is expected to apply a 1.544MHz clock signal to
this input pin. Similarly, for E1 Applications, the user is expected to apply a
2.048MHz clock signal to this input pin.
TAOS_0
69
TAOS_1
70
TAOS_2
71
TAOS_3
72
WR_R/W
69
RD_DS
70
ALE_AS
71
CS
72
NOTE: Internally pulled “Low” with a 50kΩ resistor for all channels.
I
Transmit All Ones Command Input - Channel n: (Hardware Mode ONLY)
The exact function of these input pins depend upon whether the XRT83L34
device has been configured to operate in the HOST or Hardware Modes, as
described below.
Hardware Mode Operation - Transmit All Ones Command Input - Channel
n - TAOS_n:
These input pins permits the user to command a given Channel to transmit an
"Unframed, All Ones" pattern (via the outbound DS1/E1 line signal) to the
remote terminal equipment.
Setting this pin to the logic "HIGH" level configures the Transmit Section (of
the corresponding channel) to transmit an Unframed, All Ones pattern via the
outbound DS1/E1 line signal.
Setting this pin to the logic "LOW" level, configures the Transmit Section (of
the corresponding channel) to transmit normal traffic via the outbound DS1/E1
line signal.
Host Mode Operation: These pins act as various microprocessor functions.
See “Microprocessor Interface” on page 13.
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
TXON_0
122
I
Transmitter Turn On for Channel _0
Hardware mode
Setting this pin "High" turns on the Transmit Section of Channel _0 and has no
control of the Channel_0 receiver. When TXON_0 = “0” then TTIP_0 and
TRING_0 driver outputs will be tri-stated.
NOTE: In Hardware mode only, all receiver channels will be turned on upon
power-up and there is no provision to power them off. The receive
channels can only be independently powered on or off in Host mode.
In Host mode
TXON_1
123
TXON_2
124
TXON_3
125
The TXON_n bits in the channel control registers turn each channel Transmit
section ON or OFF. However, control of the on/off function can be transferred
to the Hardware pins by setting the TXONCTL bit (bit 6) to “1” in the register at
address hex 0x42.
Transmitter Turn On for Channel _1
Transmitter Turn On for Channel _2
Transmitter Turn On for Channel _3
NOTE: Internally pulled "Low" with a 50kΩ resistor for all channels.
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