XRT83L34_05 Datasheet, PDF (16/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR INTERFACE
SIGNAL NAME
HW_HOST
PIN #
68
TYPE
I
DESCRIPTION
HOST/HARDWARE Mode Control Input pin:
This pin permits the user to configure the XRT83L34 device to operate in
either the HOST or the Hardware Mode. If the user configures the XRT83L34
device to operate in the HOST Mode, then the Microprocessor Interface
block will become active and virtually all configuration settings (within the
XRT83L34 device) will be achieved by writing values into the on-chip regis-
ters (via the Microprocessor Interface). If the user configures the XRT83L34
device to operate in the Hardware Mode, then the Microprocessor Interface
block will be disabled, and all configuration settings (within the XRT83L34
device) will be achieved by setting various input pins to logic HIGH or LOW
settings.
LOGIC LOW - Configures the XRT83L34 device to operate in the HOST
Mode.
LOGIC HIGH or FLOATING - Configures the XRT83L34 device to operate in
the Hardware Mode.
WR_R/W
NOTE: Internally pulled “High” with a 50kΩ resistor.
69
I
Write Strobe/Read-Write Operation Identifier/Transmit All Ones Input
Pin - Channel 0:
The exact function of this input pin depends upon whether the XRT83L34
device has been configured to operate in the HOST or the Hardware Mode,
as described below.
TAOS_0
69
HOST Mode Operation - Write Strobe/Read-Write Operation Identifier:
Assuming that the XRT83L34 device has been configured to operate in the
Host Mode, then the exact function of the this input pin depends upon which
mode the Microprocessor Interface has been configured to operate in, as
described below.
Intel-Asynchronous Mode - WR* - Write Strobe Input pin:
If the Microprocessor Interface is configured to operate in the Intel-Asynchro-
nous Mode, then this input pin functions as the WR* (Active-Low WRITE
Strobe) input signal from the Microprocessor. Once this active-low signal is
asserted, then the input buffers (associated with the Bi-Direction Data bus
pins, D[7:0]) will be enabled. The Microprocessor Interface will latch the con-
tents on the Bi-Directional Data Bus (into the "target" register or address
location, within the XRT83L34) upon the rising edge of this input pin.
Motorola-Asynchronous Mode - R/W* - Read/Write Operation Identifica-
tion Input pin:
If the Microprocessor Interface is operating in the "Motorola-Asynchronous"
Mode, then this pin is functionally equivalent to the R/W* input pin. In the
Motorola-Asynchronous Mode, a READ operation occurs if this pin is held at
a logic "1", coincident to a falling edge of the RD/DS* (Data Strobe) input pin.
Similarly, a WRITE operation occurs if this input is at a logic "0", coincident to
a falling edge of the RD/DS* (Data Strobe) input pin.
Hardware Mode Operation - Transmit All “Ones” Channel_0 - Hardware
Mode
See “Transmit All Ones Command Input - Channel n: (Hardware
Mode ONLY)” on page 12.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
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