XRT83L34_05 Datasheet, PDF (18/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
ALE_AS
TAOS_2
PIN #
71
71
TYPE
I
DESCRIPTION
Address Latch Enable/Address Strobe/Transmit All Ones Input - Chan-
nel 2:
The exact function of this input pin depend upon whether the XRT83L34
device has been configured to operate in the HOST or Hardware Mode, as
described below.
HOST Mode Operation - Address Latch Enable/Address Strobe Input
Pin:
The exact function of this input pin depends upon which mode the Micropro-
cessor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - ALE - Address Latch Enable:
If the Microprocessor Interface (of the XRT83L34 device) has been config-
ured to operate in the Intel-Asynchronous Mode, then this active-high input
pin is used to latch the address (present at the Microprocessor Interface
Address Bus pins (A[6:0]) into the XRT83L34 Microprocessor Interface bloc
and to indicate the start of a READ or WRITE cycle.
Pulling this input pin "high" enables the input bus drivers for the Address Bus
Input pins (A[6:0]). The contents of the Address Bus will be latched into the
XRT83L34 Microprocessor Interface circuitry, upon the falling edge of this
input signal.
Motorola Asynchronous Mode - AS* - Address Strobe Input:
If the Microprocessor Interface has been configured to operate in the Motor-
ola-Asynchronous Mode, then pulling this input pin "LOW enables the "input"
bus drivers for the Address Bus Input pins.
During each READ or WRITE operation, the user is expected to drive this
input pin "LOW" after (or around the time that) he/she has places the address
(of the "target" register) onto the Address Bus pins (A[6:0]). The user is then
expected to hold this input pin "LOW" for the remainder of the READ or
WRITE cycle.
NOTE: It is permissible to tie the ALE_AS* and CS* input pins together..
Read and Write operations will be performed properly if ALE_AS is
driven "LOW" coincident to whenever CS* is also driven "LOW".
CS
TAOS_3
Hardware Mode Operation - Transmit All “Ones” Channel_2 - Hardware
Mode
See “Transmit All Ones Command Input - Channel n: (Hardware
Mode ONLY)” on page 12.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
72
I
Chip Select Input/Transmit All Ones Input - Channel 3:
The exact function of this input pin depends upon whether the XRT83L34
72
device has been configured to operate in the HOST or Hardware Mode, as
described below.
HOST Mode Operation - Chip Select Input pin:
The user must assert this active-low signal in order to select the Micropro-
cessor Interface for READ and WRITE operations between the Microproces-
sor and the XRT83L34 on-chip registers.
Hardware Mode Operation - Transmit All Ones Input - Channel 3:
See “Transmit All Ones Command Input - Channel n: (Hardware
Mode ONLY)” on page 12.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
15