XRT83L34_05 Datasheet, PDF (82/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 36: MICROPROCESSOR REGISTER #64, BIT DESCRIPTION
REGISTER ADDRESS
1000000
BIT #
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
D7
SR/DR Single-rail/Dual-rail Select: Writing a “1” to this bit configures R/W
0
all 8 channels in the XRT83L34 to operate in the Single-rail
mode.
Writing a “0” configures the XRT83L34 to operate in Dual-rail
mode.
D6
ATAOS Automatic Transmit All Ones Upon RLOS: Writing a “1” to
R/W
0
this bit enables the automatic transmission of All "Ones" data
to the line for the channel that detects an RLOS condition.
Writing a “0” disables this feature.
D5
RCLKE Receive Clock Edge: Writing a “1” to this bit selects receive
R/W
0
output data of all channels to be updated on the negative edge
of RCLK.
Wring a “0” selects data to be updated on the positive edge of
RCLK.
D4
TCLKE Transmit Clock Edge: Writing a “0” to this bit selects transmit R/W
0
data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all
channels to be sampled on the falling edge of TCLK_n.
Writing a “1” selects the rising edge of the TCLK_n for sam-
pling.
D3
DATAP DATA Polarity: Writing a “0” to this bit selects transmit input
R/W
0
and receive output data of all channels to be active “High”.
Writing a “1” selects an active “Low” state.
D2
Reserved
0
D1
GIE
Global Interrupt Enable: Writing a “1” to this bit globally
R/W
0
enables interrupt generation for all channels.
Writing a “0” disables interrupt generation.
D0
SRESET Software Reset µP Registers: Writing a “1” to this bit longer R/W
0
than 10µs initiates a device reset through the microprocessor
interface. All internal circuits are placed in the reset state with
this bit set to a “1” except the microprocessor register bits.
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