XRT83L34_05 Datasheet, PDF (76/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 26: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION
REGISTER ADDRESS
0000110
0010110
0100110
0110110
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
RO
0
D6
DMOIS_n Driver Monitor Output Interrupt Status: This bit is set to a
RUR
0
“1” every time the DMO status has changed since last read.
NOTE: This bit is reset upon read.
D5
FLSIS_n FIFO Limit Interrupt Status: This bit is set to a “1” every time RUR
0
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) sta-
tus has changed since last read.
NOTE: This bit is reset upon read.
D4
LCVIS_n Line Code Violation Interrupt Status: This bit is set to a “1” RUR
0
every time when LCV status has changed since last read.
NOTE: This bit is reset upon read.
D3
NLCDIS_n Network Loop-Code Detection Interrupt Status: This bit is RUR
0
set to a “1” every time when NLCD status has changed since
last read.
NOTE: This bit is reset upon read.
D2
AISDIS_n AIS Detection Interrupt Status: This bit is set to a “1” every RUR
0
time when AISD status has changed since last read.
NOTE: This bit is reset upon read.
D1
RLOSIS_n Receive Loss of Signal Interrupt Status: This bit is set to a RUR
0
“1” every time RLOS status has changed since last read.
NOTE: This bit is reset upon read.
D0
QRPDIS_n Quasi-Random Pattern Detection Interrupt Status: This bit RUR
0
is set to a “1” every time when QRPD status has changed
since last read.
NOTE: This bit is reset upon read.
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