XRT83L34_05 Datasheet, PDF (66/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR REGISTER DESCRIPTIONS
TABLE 20: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION
REGISTER ADDRESS
0000000
0010000
0100000
0110000
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
R/W
0
D6
Reserved
R/W
D5
RXON_n Receiver ON: Writing a “1” into this bit location turns on the
R/W
0
Receive Section of channel n. Writing a “0” shuts off the
Receiver Section of channel n.
NOTES:
1. This bit provides independent turn-off or turn-on
control of each receiver channel.
2. In Hardware mode all receiver channels are always
on.
D4
EQC4_n Equalizer Control bit 4: This bit together with EQC[3:0] are
R/W
0
used for controlling transmit pulse shaping, transmit line build-
out (LBO) and receive monitoring for either T1 or E1 Modes of
operation.
See Table 5 for description of Equalizer Control bits.
D3
EQC3_n Equalizer Control bit 3: See bit D4 description for function of R/W
0
this bit
D2
EQC2_n Equalizer Control bit 2: See bit D4 description for function of R/W
0
this bit
D1
EQC1_n Equalizer Control bit 1: See bit D4 description for function of R/W
0
this bit
D0
EQC0_n Equalizer Control bit 0: See bit D4 description for function of R/W
0
this bit
63