XRT83L34_05 Datasheet, PDF (62/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
8. After waiting the appropriate time for the data (on the bi-directional data bus) to settle and can be safely
accepted by the Microprocessor, the XRT83L34 device will indicate that this data can now be latched into
the "target" address location by toggling the "RDY*/DTACK*" output pin "LOW.
9. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it
can then terminate the WRITE cycle by toggling the "RD*/DS*" (Data Strobe) input pin "HIGH".
NOTE: Once the user toggles the "RD*/DS* (Data Strobe) input pin "HIGH", then the following two things will happen.
1. The XRT83L34 device will latch the contents of the bi-directional data bus into the Microprocessor Inter-
face block.
2. The XRT83L34 device will terminate the "WRITE" cycle.
Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during a "Motorola-
Asynchronous" Write Operation.
FIGURE 28. ILLUSTRATION OF A MOTOROLA-ASYNCHRONOUS WRITE OPERATION
Microprocessor places “target”
Address value on A[6:0]
ALE/AS*
A[6:0]
CS*
Address of Target Register
D[7:0]
Data to be Written
RD*/DS*
WR/R/W*
RDY*/DTACK*
Write Operation is
Terminated Here
Address Decoding
Circuitry asserts
CS*
Write Operation begins
Here
DTACK* toggles “low” to indicate
That valid data can be latched into
Microprocessor toggles “R/W*” low ^{“target” Address location of chip}
To Denote WRITE operation
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