XRT83L34_05 Datasheet, PDF (23/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
CLOCK SYNTHESIZER
SIGNAL NAME
MCLKE1
CLKSEL0
CLKSEL1
CLKSEL2
PIN #
32
37
38
39
TYPE
I
I
DESCRIPTION
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty
cycle of 40% to 60% can be provided at this pin.
In systems that have only one master clock source available (E1 or T1), that
clock should be connected to both MCLKE1 and MCLKT1 inputs for proper
operation.
NOTES:
1. All channels of the XRT83L34 must be operated at the same clock
rate, either T1, E1 or J1.
2. Internally pulled “Low” with a 50kΩ resistor.
Clock Select inputs for Master Clock Synthesizer - Hardware mode
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that
can be used to generate a master clock from an accurate external clock
source according to the following table.
The MCLKRATE control signal is generated from the state of EQC[4:0]
inputs. See Table 4 for description of Transmit Equalizer Control bits.
Host Mode: The state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits. See register address
1000001.
MCLKE1 MCLKT1
(kHz)
(kHz)
2048
2048
2048
2048
2048
1544
1544
1544
1544
1544
2048
1544
8
X
8
X
16
X
16
X
56
X
56
X
64
X
64
X
128
X
128
X
256
X
256
X
CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
CLKOUT
(KHz)
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
NOTE: These pins are internally pulled "Low" with a 50kΩ resistor.
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