XRT83L34_05 Datasheet, PDF (27/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
SIGNAL NAME
TERSEL0
TERSEL1
PIN #
113
112
TYPE
I
DESCRIPTION
Termination Impedance Select pin 0
Termination Impedance Select pin 1
In the Hardware mode and in the internal termination mode (TXTSEL=”1”
and RXTSEL=”1”), TERSEL[1:0] control the transmit and receive termination
impedance according to the following table.
TERSEL1 TERSEL0 Termination
0
0
100Ω
0
1
110Ω
1
0
75Ω
1
1
120Ω
In the internal termination mode, the receiver termination of each receiver
is realized completely by internal resistors or by the combination of internal
and one fixed external resistor (see description of RXRES[1:0] pins).
In the internal termination mode the transformer ratio of 1:2 and 1:1 is
required for transmitter and receiver respectively with the transmitter output
AC coupled to the transformer.
NOTES:
1. This pin is internally pulled "Low" with a 50kΩ resistor.
2. In Hardware Mode all channels share the same TERSEL control
function.
ICT
120
I
In-Circuit Testing (active "Low"):
When this pin is tied “Low”, all output pins are forced to a “High” impedance
state for in-circuit testing.
Pulling RESET and ICT pins “Low” simultaneously will put the chip in factory
test mode. For normal operation, the user should either leave this input pin
"floating" or pull it to a logic "HIGH" level.
NOTE: Internally pulled “High” with a 50kΩ resistor.
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