XRT83L34_05 Datasheet, PDF (6/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
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REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 7: RECEIVE TERMINATIONS ........................................................................................................ 37
Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) .............. 37
Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) .................... 38
TRANSMITTER (CHANNELS 0 - 3) .............................................................................................................. 38
Transmit Termination Mode ........................................................................................................................ 38
TABLE 8: TRANSMIT TERMINATION CONTROL ........................................................................................ 38
TABLE 9: TERMINATION SELECT CONTROL ............................................................................................ 38
External Transmit Termination Mode .......................................................................................................... 38
TABLE 10: TRANSMIT TERMINATION CONTROL ...................................................................................... 39
TABLE 11: TRANSMIT TERMINATIONS .................................................................................................... 39
REDUNDANCY APPLICATIONS ............................................................................................................... 39
TYPICAL REDUNDANCY SCHEMES ....................................................................................................... 40
Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ........ 41
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............... 41
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy .......................... 42
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy ............................ 43
PATTERN TRANSMIT AND DETECT FUNCTION ................................................................................................. 44
TABLE 12: PATTERN TRANSMISSION CONTROL....................................................................................... 44
TRANSMIT ALL ONES (TAOS) ....................................................................................................................... 44
NETWORK LOOP CODE DETECTION AND TRANSMISSION................................................................................. 44
TABLE 13: LOOP-CODE DETECTION CONTROL ...................................................................................... 44
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ........................................................... 45
LOOP-BACK MODES...................................................................................................................................... 46
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ......................................................................... 46
TABLE 15: LOOP-BACK CONTROL IN HOST MODE................................................................................... 46
LOCAL ANALOG LOOP-BACK (ALOOP).......................................................................................................... 46
Figure 20. Local Analog Loop-back signal flow............................................................................. 46
REMOTE LOOP-BACK (RLOOP) .................................................................................................................... 47
Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path .................. 47
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path ............... 47
DIGITAL LOOP-BACK (DLOOP) ..................................................................................................................... 48
Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ................. 48
DUAL LOOP-BACK ........................................................................................................................................ 48
Figure 24. Signal flow in Dual loop-back mode.............................................................................. 48
THE MICROPROCESSOR INTERFACE............................................................................ 49
THE PINS OF THE MICROPROCESSOR INTERFACE ............................................................................................ 49
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ............................................................ 49
OPERATING THE MICROPROCESSOR INTERFACE IN THE INTEL-ASYNCHRONOUS MODE ...................................... 52
TABLE 17: THE ROLES OF THE VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OP-
ERATE IN THE INTEL-ASYNCHRONOUS MODE.............................................................................. 52
CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE INTEL-ASYNCHRONOUS MODE .............. 53
THE INTEL-ASYNCHRONOUS READ CYCLE ....................................................................................................... 53
Figure 25. Illlustration of an Intel-Asynchronous Mode Read Operation .................................... 54
THE INTEL-ASYNCHRONOUS WRITE CYCLE...................................................................................................... 54
Figure 26. Illustration of an Intel-Asynchronous Mode Write Operation ..................................... 55
OPERATING THE MICROPROCESSOR INTERFACE IN THE MOTOROLA-ASYNCHRONOUS MODE .......................... 55
.................................................................................................................................................................... 56
TABLE _, THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE
MOTOROLA-ASYNCHRONOUS MODE................................................................................................................ 56
CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE MOTOROLA-ASYNCHRONOUS MODE....... 57
THE MOTOROLA-ASYNCHRONOUS READ-CYCLE:.............................................................................................. 57
Figure 27. Illlustration of a Motorola-Asynchronous Mode Read Operation............................... 58
THE MOTOROLA-ASYNCHRONOUS WRITE CYCLE............................................................................................. 58
Figure 28. Illustration of a Motorola-Asynchronous Write Operation.......................................... 59
MICROPROCESSOR REGISTER TABLES .......................................................................................................... 60
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