XRT83L34_05 Datasheet, PDF (22/99 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JITTER ATTENUATOR
SIGNAL NAME
JASEL0
JASEL1
PIN #
58
57
TYPE
I
DESCRIPTION
Jitter Attenuator Select Pins - Hardware Mode
Jitter Attenuator select pin 0
Jitter Attenuator select pin 1
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path,
the receive path or to disable it.
JASEL1 JASEL0 JA Path
0
0
Disabled
0
01
Transmit
01
10
Receive
01
1
Receive
JAJABWBWHz
T1 ^MHz E1
-T--1-- -E--1--
3
10
3
10
3
1.5
FIFO Size
T--1--/-E--1-
32/32
32/32
64/64
A[6]
57
A[5]
58
Microprocessor Address Bits A[6:5] -Host Mode
See “Address Bus Input Pins/Jitter Attenuator Select Input Pins/
Equalizer Control Input pins:” on page 18.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
19