HB52R329E22-F Datasheet, PDF (7/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
0 0 0 0 0 0 0 1 01
0
W latency
21
SDRAM device attributes
0 0 0 1 0 1 1 0 16
Registered
22
SDRAM device attributes:
General
0 0 0 0 1 1 1 0 0E
V_CC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6F) 10 ns
1 0 1 0 0 0 0 0 A0
CL = 2
(-B6F) Undefined
0 0 0 0 0 0 0 0 00
24
SDRAM access from Clock
0 1 1 0 0 0 0 0 60
(2nd highest CE latency)
(-A6F) 6 ns
CL = 2
(-B6F) Undefined
0 0 0 0 0 0 0 0 00
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
0 0 0 0 0 0 0 0 00
26
SDRAM access from Clock
0 0 0 0 0 0 0 0 00
(3rd highest CE latency)
Undefined
27
Minimum row precharge time 0 0 0 1 0 1 0 0 14
20 ns
28
Row active to row active min 0 0 0 1 0 1 0 0 14
20 ns
29
RE to CE delay min
0 0 0 1 0 1 0 0 14
20 ns
30
Minimum RE pulse width
0 0 1 1 0 0 1 0 32
50 ns
31
Density of each bank on module 0 0 1 0 0 0 0 0 20
2 bank
128M byte
32
Address and command signal 0 0 1 0 0 0 0 0 20
input setup time
2 ns*³
33
Address and command signal 0 0 0 1 0 0 0 0 10
input hold time
1 ns*³
34
Data signal input setup time 0 0 1 0 0 0 0 0 20
2 ns*³
35
Data signal input hold time
0 0 0 1 0 0 0 0 10
1 ns*³
36 to 61 Superset information
0 0 0 0 0 0 0 0 00
Future use
62
SPD data revision code
0 0 0 1 0 0 1 0 12
Rev. 1.2A
63
Checksum for bytes 0 to 62
0 0 1 1 0 1 1 1 37
55
(-A6F)
(-B6F)
0 0 1 1 0 1 0 1 35
53
64
Manufacturer’s JEDEC ID code 0 0 0 0 0 1 1 1 07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00
Data Sheet No. E0112H10
7