HB52R329E22-F Datasheet, PDF (58/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Mode Register Set Cycle
CK
CKE
S
RE
;;;;;;;;;;;;;; CE
W
BA
;;;;;;;;;;;;;;;;;;;;;; Address
DQMB
Dout
;_; ^Din
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
V_IH
valid
code R: b
C: b
C: b’
Precharge
If needed
l _RP
l _RSA
Mode Bank 3
register Active
Set
l _RCD
High-Z
Bank 3
Read
b
Output mask
b+3 b’ b’+1 b’+2 b’+3
l RCD = 3
CE latency = 4
Burst length = 4
IH ^{= V} IL ^{or V}
Read Cycle/Write Cycle
; _CK
CKE
S
RE
CE
W
BA
Address
DQMB
Dout
Din
CKE
;;;;;;;;;; S
RE
CE
W
BA
Address
DQMB
Dout
Din
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
V_IH
Read cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= V_IH or V_IL
R:a
Bank 0
Active
V_IH
C:a
R:b
C:b
C:b'
C:b"
Bank 0
Read
Bank 3
Active
a a+1 a+2 a+3
b b+1 b+2 b+3 b'
High-Z
Bank 3 Bank 0
Read Precharge
Bank 3
Read
Bank 3
Read
b'+1 b" b"+1 b"+2 b"+3
Bank 3
Precharge
Write cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= V_IH or V_IL
R:a
Bank 0
Active
C:a
R:b
C:b
C:b'
C:b"
High-Z
a
Bank 0
Write
a+1 a+2 a+3
b b+1 b+2 b+3 b'
Bank 3
Active
Bank 3
Write
Bank 0
Precharge
Bank 3
Write
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
Data Sheet No. E0112H10
58