HB52R329E22-F Datasheet, PDF (19/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Notes: 1. AC measurement assumes t_T = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C_L = 50 pF.
3. t_LZ (max) defines the time at which the outputs achieves the low impedance state.
4. t_HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t_CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
• Ambient illuminance: Under 100 lx
input
2.4 V
2.0 V
0.4 V ^{0.8 V}
t_T
t_T
DQ
CL
Data Sheet No. E0112H10
19