HB52R329E22-F Datasheet, PDF(5/66 Page) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F Datasheet, PDF (5/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F

Pin Description

Pin name

Function

A0 to A11

Address input

ï£§ Row address

A0 to A11

ï£§ Column address

A0 to A9

A13/A12

Bank select address

BA0/BA1

DQ0 to DQ63

Data input/output

CB0 to CB7

Check bit (Data input/output)

S0 to S3

Chip select input

Row enable (RAS) input

Column enable (CAS) input

Write enable input

DQMB0 to DQMB7

Byte data mask

CK0 to CK3

Clock input

CKE0

Clock enable input

Write protect for serial PD

REGE*1

SDA

Data input/output for serial PD

SCL

Clock input for serial PD

SA0 to SA2

Serial address input

VCC

Primary positive power supply

VSS

Ground

No connection

Note: 1. REGE is the Register Enable pin which permits the DIMM to operate in âbufferedâ mode and

âregisteredâ mode. To conform to this specification, mother boards must pull this pin to high state

(âregisterdâ mode).

Data Sheet No. E0112H10

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