HB52R329E22-F Datasheet, PDF(55/66 Page) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F Datasheet, PDF (55/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F

Initialization sequence: When 200 Âµs or more has past after the above power-up sequence, all banks must be

precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF).

Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping

DQMB to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention

on memory system formed with a number of device.

Stabilization time: The PLL requires a stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required following power-up. So this SDRAM module needs

dammy cycle for 50 Âµs after power-up.

Power up sequence

100 Âµs

VCC 0 V

CKE, DQMB Low

CK Low

S, DQ Low

Power stabilize

Initialization sequence

200 Âµs

Data Sheet No. E0112H10

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