HB52R329E22-F Datasheet, PDF (43/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less than
1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
READ to WRITE Command Interval (1)
CK
Command
CL=3
DQMB
CL=4
Din
Dout
READ WRIT
in B0 in B1 in B2 in B3
High-Z
READ to WRITE Command Interval (2)
Burst Length = 4
Burst write
CK
Command
DQMB
CL=3
Dout
CL=4
Din
READ
WRIT
2 clock
High-Z
High-Z
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set High so that
the output buffer becomes High-Z before data input.
Data Sheet No. E0112H10
43