HB52R329E22-F Datasheet, PDF(29/66 Page) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F Datasheet, PDF (29/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F

Current state

S RE CE W Address Command

Operation

Write with auto-

precharge

HÃ

DESL

Continue burst to end and

precharge

NOP

Continue burst to end and

precharge

BST

ILLEGAL

BA, CA, A10 READ/READ A ILLEGAL*4

BA, CA, A10 WRIT/WRIT A ILLEGAL*4

H H BA, RA

ACTV

Other bank active

ILLEGAL on same bank*3

H L BA, A10

PRE, PALL

ILLEGAL*4

HÃ

REF, SELF

ILLEGAL

MODE

MRS

ILLEGAL

Refresh

(auto-refresh)

HÃ

DESL

Enter IDLE after tRC

NOP

Enter IDLE after tRC

BST

Enter IDLE after tRC

BA, CA, A10 READ/READ A ILLEGAL*5

BA, CA, A10 WRIT/WRIT A ILLEGAL*5

H H BA, RA

ACTV

ILLEGAL*5

H L BA, A10

PRE, PALL

ILLEGAL*5

HÃ

REF, SELF

ILLEGAL

MODE

MRS

ILLEGAL

Notes: 1. H: VIH. L: VIL. Ã: VIH or VIL.

The other combinations are inhibit.

2. An interval of tDPL is required between the final valid data input and the precharge command.

3. If tRRD is not satisfied, this operation is illegal.

4. Illegal for same bank, except for another bank.

5. Illegal for all banks.

6. NOP for same bank, except for another bank.

Data Sheet No. E0112H10

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