HB52R329E22-F Datasheet, PDF (33/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode
register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9 A8: (OPCODE): The SDRAM module has two types of write modes. One is the
burst write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CE latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
OPCODE
0
LMODE
BT
BL
A6 A5 A4 CAS Latency
00 0
R
A3 Burst Type
0 Sequential
Burst Length
A2 A1 A0 _{BT=0 BT=1}
00 1
R
1 Interleave
00 0 1
1
01 0
3*
00 1 2
2
01 1
4
01 0 4
4
1XX
R
01 1 8
8
10 0 R
R
A13 A12 A11 A10 ^A9
0 0 0 00
X X X X0
X X X X1
X X X X1
Note: Only -6A.
A8 Write mode
0 Burst read and burst write
1
R
0 Burst read and single write
1
R
10 1 R
R
11 0 R
R
1 1 1 F.P. R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
Data Sheet No. E0112H10
33