HB52R329E22-F Datasheet, PDF (37/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address (BA) specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 1 clock).
CK
Command
Address
Din
t _RCD
ACTV
WRIT
Row
Column
in 0
Auto Precharge
Read with auto-precharge: In this operation, since precharge is automatically performed after completing a
read operation, a precharge command need not be executed after each read operation. The command executed
for the same bank after the execution of this command must be the bank active (ACTV) command. In addition,
an interval defined by l_APR is required before execution of the next command.
CE latency
4
3
Precharge start cycle
2 cycle before the final data is output
1 cycle before the final data is output
Burst Read (Burst Length = 4)
CK
CL=3 Command
Dout
CL=4 Command
Dout
ACTV
ACTV
lRAS
READ A
lRAS
READ A
ACTV
out0
out1
out2
out3
l_APR = 0
ACTV
out0
out1
out2
out3
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of t_RAS (l_RAS) is required between previous active (ACTV) command and internal precharge " ".
l_APR = 0
Data Sheet No. E0112H10
37