HB52R329E22-F Datasheet, PDF (44/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less than
1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the read
command is executed.
WRITE to READ Command Interval (1)
CK
Command
DQMB
Din
Dout
WRIT READ
in A0
Column = A
Write _{Column = B}
Read
WRITE to READ Command Interval (2)
out B0 out B1
CE Latency
Column = B
Dout
out B2 out B3
Burst Write Mode
CE Latency = 3
Burst Length = 4
Bank 0
CK
Command
WRIT
READ
DQMB
Din
in A0
in A1
Dout
Column = A
Write
Column = B
Read
out B0 out B1
CE Latency
Column = B
Dout
out B2 out B3
Burst Write Mode
CE Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commandscannot
be executed; it is necessary to separate the two commands with a precharge command and a bank-active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data
will continue to be written until one clock before the read command is executed (as in the case of the same bank
and the same address).
Data Sheet No. E0112H10
44